1. Field of the Invention
The invention relates to an integrated delay circuit, more particularly an integrated delay circuit adapted to very high speeds, for instance greater than 1 Gigabit per second, and more particularly suitable for integration into a III-V semiconductor such as gallium arsenide (GaAs). In this application, the delay circuit may be made of field effect transistors, and especially those of the MESFET (metal semiconductor field effect transistor) and then more particularly suited for logic of the DCFL type (direct-coupled FET logic) including BDCFL (buffered DCFL). It may also be made with field effect transistors of the HEMT type (high-electron-mobility transistor) that are integrated into a ternary semiconductor material, such as gallium arsenide and aluminum, of the AlGaAs/GaAs type, for example. It will be seen as well that the invention is equally applicable to differential amplifiers, with bipolar transistors but more advantageously with MESFET transistors with SCFL logic (source-coupled FET logic). The delay circuit according to the invention can easily be linearly adjusted and is applicable more particularly to very high-speed transmission systems and to information processing systems that also employ very high-speed transmissions.
2. Description of the Related Art
Delay circuits including an amplifier, one terminal of which is connected to a central block controlling the variation in the delay by adjusting the current furnished by the amplifier, are well known and widely used. The control blocks are currently made of RC circuits, and adjustment of the delay is done by varying the value of the resistance and/or the capacitance of the RC circuits. In an integrated circuit with field effect transistors, for example of the MOS type (metal oxide semiconductor), the resistance and the capacitance are ordinarily constituted by transistors.
The disadvantage of such delay circuits is the exponential curve in the variation of the delay with respect to the variation in the values of R and C. The linearity of the delay adjustment accordingly requires RC products with high values, which are incompatible with very short delay times. On the other hand, the RC circuits must be inserted between input and output buffer circuits in order to make the external circuits insensitive to the variations in R and C. Furthermore, the technology for manufacturing field effect transistors produces pronounced drift in the characteristics of the transistors of different integrated circuits. This drift is an obstacle to the reliability and sensitivity of the current adjustment sought.
In certain cases, such as the very high frequency phase-locked loop circuit described in European Patent Disclosure EP 0 441 684 and the high-output digital transmission system described in European Patent Disclosures EP-A 0 466 591, EP-A 0 466 592 and EP-A 0 466 593, it is currently necessary to use very short adjustable delays. By way of example, the aforementioned circuit and system may require delays that are adjustable by increments of only a few picoseconds each. Moreover, the linearity in the variation of these delays is a condition that facilitates control and considerably improves its performance. On the other hand, these delay circuits must be very compact and highly adaptable to high-speed technologies, such as those made with field-effect transistors and more particularly those integrated into a III-V semiconductor. In this latter application, DCFL logic offers the advantage of very simple and very fast logic gates, made of only two transistors connected in series between the supply potentials, and of low energy consumption at a low supply voltage, ordinarily 2 V. On the other hand, it has the disadvantage of asymmetrical switching times, where the rise time is markedly different from the fall or decay time. BDCFL logic overcomes this disadvantage, at the cost merely of adding two further series-connected transistors between the supply potentials. Both these logic systems will be called the DCFL type.
Delay circuits made of complementary-type transistors are known, such as CMOS (complementary MOS) delay circuits. However, they cannot be transposed to DCFL-type logic, since that is not a logic made with complementary transistors. On the other hand, the present Applicant, in its European Patent Applications EP-A 0 493 149 and EP-A 0 493 150, has already described delay circuits made with differential amplifiers, making it possible to obtain substantially linear delays. These delay devices lend themselves well to bipolar ECL (emitter coupled logic) or CML (current-mode logic) technology, integrated into the monocrystalline silicon. However, these circuits cannot be transposed to logic of the DCFL type, since it does not have a differential structure.